MIPS Subset Implementation: In Simple Language

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Let us begin the implementation of the subset in easy terms. The single long clock cycle is the easiest and the basic term to study. In this, only one clock edge is used for the execution of the instructions and their completion on the next edge of the clock.

No doubt the approach is easy to comprehend and understand, but there is no practicality of the approach. It is because of the slow speed of the implementation. The different numbers of clock cycles are used for determining the instructions. Each of the clock cycle and the instructions have to be shorter. The implementation of the subset is realistic, but the control has to be complex. See the control of the logic equations and the specifications of the finite state machine. The process of synthesizing the hardware implementation is with the modern CAD system.

Before going further, it would be better if you give a read to the introduction of the processor datapath and control.

Building a Data Path

The process can be best started with the examination of the major components which are needed for the MIPS instruction of all the types. There is also the requirement of seeing the datapath elements for every instruction. Along with this, building the sections in the data path and the elements, then we need to select the control signals. After this process, we do not need to add the control signals in the actual data path. But it happens until the control unit has been added.

There are various elements which are needed to build the data path.

  1. The place which is needed for storing the program instructions is the first element.
  2. Second is the one which is a state element, and it is the memory unit. This is the element which is used for holding and supply of the instructions in the given address location. It also needed to be kept in the state element. The name of the location is the program counter.
  3. The adder is the third element needed in the process. And it has to be combinational. The best part is that it can be built from the ALU. The process of building them is easy as it begins by wiring the control lines. The result is the control which always specifies the add operation.

Execution of instruction

It begins by fetching the instruction from memory. Then the next instruction has to be prepared for execution and this the program counter has to be incremented. Pointing at the next instruction and that too after 4 bytes.

R-format instructions

The basic function of the format instructions is to read the two registers. The other function is the performance of the operation by the arithmetic logic unit on the registers’ contents. After this, it has to write the result. The other name of the instruction is either arithmetic-logical instructions or R-type instructions.

The class where the instructions are stored are added, sub, and, or and slt.

For example, we have the instruction- add $3, $4, $5, which reads $5 and $4 after writing $3. 32 registers of the processors have to be stored in a structured format, and it is named a register file.

Register file

The file which contains the collection of registers for reading and writing them by the other specified number of registers that are present in the file is called register file. The register state of the machine is present in the register file. What else do we need? It is the arithmetic logic unit to perform the operations on the already read values present in the registers.

As we know that the R-format instructions contain three register operands, then we need to look for reading the two data words from the file. Also, writing the one data word from the register file is also important.

Reading a data word

For the process of reading the registers from the file to happen, we need input to the register file and output from the register file. The basic operation which the first need (input) performs is the specification of the register number which is to be read from the register file.

Writing a data word

For writing a data word into the file, there is the requirement of two inputs. The first would specify the number of the register which has to be written. For the purpose of supplying the data which are to written into the register, the other input is required.

All in all, we need four inputs and two outputs. Doing the output of the content which are on the register numbers is the function of the register file. These are the numbers which are present on the read register inputs. The write control signal, as the name suggests controls the writing part. Every time the clock input falls, the writing is asserted. For the specification of one of two registers, we need register number inputs of 5 bits. The two values, the data input and the data output, have a width of 32 bits each. Similarly, 32 bits are taken by the ALU,and these are used for the production of 32 bits’ result.

MIPS load and store instructions

The general form of these instructions is:

1w $1, offset_value ($2) or sw $1, offset_value ($2)

These are used for the computation of the memory address. It does this by adding the base register to the signed offset field of 16 bits.

  1. Instruction is a store-

This is the field which contains the instruction. The value which has to be stored in the case of the stored instruction, then it has to be read from the register file.

  1. Instruction is a load-

In this case, the register file must get the value written in the specified register which is read from memory.

Beq instruction

There are three operands of this instruction followed by two registers. The latter part is compared for equality. For the computation of the branch target address relative to the instruction address by the branch, the 16-bit offset is used.

For example, beq $1, $2, offset.

Its implementation takes place with the process of computation of the branch target address. It goes well with the addition of the offset field instruction extended with a sign to the program counter.

Details to be taken care of in the instruction set architecture

  1. The base for the branch address calculation can be termed in simple language as the address of the instruction which follows the branch. The instruction set architecture specifies it. Usage of the value as the base for the computation of the branch target address has become easy. It has been possible by the computation of the address of the next instruction as PC+4.
  2. There is a 2bit left shift of the offset field, and the architecture states it. It happens because of the word offset in the architecture. It is one of the most useful shifts in the architecture as it is able to multiply the effective range of the offset field.

For dealing with the complication which we have discussed in the second detail needs to be shifted in the offset field by two. The next thing we need to do is the determination of the sequence of the instruction at the branch target address. Every time the condition of the process is true, the program counter gets the branch target address. Also, the current PC is replaced with the incremented PC. This is the case in which we can say that the branch is not taken.